Variable capacity diode fabrication method with selective diffusion of junction region impurities

ABSTRACT

A VARIABLE CAPACITY DIODE WTH A HYPERABRUPT P-N JUNCTION IS FABRICATED BY CUTTING A HOLE THOROUGH AN OXIDE COATING ATOP A P-TYPE SEMICONDUCTOR LAYER EPITAXIALLY GROWN ON A MORE HEAVILY DOPED P-TYPE SEMICONDUCTOR SUBSTRATE, INTO THE EPITAXIALLY GROWN LAYER. A STRONGLY NTYPE REGION CONTAINING BOTH DONOR IMPURITIES AND FASTER DIFFUSING ACCEPTOR IMPURITIES IS THEN GROWN EPITAXIALLY IN THE HOLE FROM THE SEMICONDUCTOR AT THE BOTTOM OF THE HOLE. THE SUBSTRATE IS THEN HEATED TO CAUSE THE MORE RAPIDLY DIFFUSING ACCEPTOR IMPURITIES TO DIFFUSE INTO THE EPITAXIALLY GROWN LAYER AHEAD OF THE MORE SLOWLY DIFFUSING DONOR IMPURITIES AND FORM A NARROW REGION OF P+ CONDUCTIVITY, RESULTING IN THE DESIRED N+P+PP+ STRUCTURE.

an. 26, W. E. E N G E L VARIABLE CAPACITY DIODE FABRICATION METHOD WITHSELECTIVE N REGION IMPURITIES 18, 1968 A n' I A @MW/fo I /lv VEN ron:

WILL/AM E. ENGELER, l

H/s. ArroRA/EY United States Patent O VARIABLE CAPACITY DIODEFABRICATION METHOD WITH SELECTIVE DIFFUSION OF JUNCTION REGIONIMPURITIES William E. Engeler, Scotia, N.Y., assignor to GeneralElectric Company, a corporation of New York Filed Sept. 18, 1968, Ser.No. 760,613 Int. Cl. H011 7/44 U.S. Cl. 148--175 16 Claims ABSTRACT OFTHE DISCLOSURE A variable capacity diode with a hyperabrupt P-N junctionis fabricated by cutting a hole thorugh an oxide coating atop a P-typesemiconductor layer epitaxially grown on a more heavily doped P-typesemiconductor substrate, into the epitaxially grown layer. A strongly N-type region containing both donor impurities and faster diffusingacceptor impurities is then grown epitaxially in the hole from thesemiconductor at the bottom of the hole. The substrate is then heated tocause the more rapidly dilfusing acceptor impurities to diffuse into theepitaxially grown layer ahead of the more slowly diffusing donorimpurities and form a narrow region of P+ conductivity, resulting in thedesired N+P+PP+ structure.

INTRODUCTION This invention relates to fabrication of variable capacitydiodes, and more particularly to a method of fabricating a variablecapacity junction diode having a hyperabrupt junction wherein a portionof the junction region is formed by selective diffusion of impuritiestherein.

A variable capacity diode may be described, generally, as asemiconductor P-N junction wherein reverse voltage applied theretoappears substantially across a region depleted of mobile chargecarriers. As amplitude of reverse voltage changes, the width of thisdepletion region also changes in direct relation thereto. Since thedepletion region acts as an insulator, the diode displays a capacitancewhich varies in an inverse manner with amplitude of applied voltage.

The degree of dependence of P-N junction capacitance upon amplitude ofapplied voltage depends on distribution of impurities in the junctionregion; that is, by lightly doping one side of the junction, thedependency of depletion width on applied voltage increases. Accordingly,if all other factors were equal, the diode having the lowest impurityconcentration in the depletion region would eX- hibit the capacitance ofhighest voltage sensitivity. However, the sensitivity of capaci-tance tovoltage also depends upon initial capacitance of the device at zeroapplied voltage. If the depletion width at zero applied voltage is madeas small as possible, maximum change in capacitance occurs when avoltage is applied; that is, the ratio of capacitance at low voltage tocapacitance at high voltage is maximized. At zero applied voltage, thedepletion width due to the inherent electric eld at the junction alsovaries in an inverse manner with impurity concentration. A highconcentration of impurities in the depletion region extant at zeroapplied voltage is therefore desirable in order tol achieve a minimumdepletion width at this voltage. Both a large degree of dependency ofdepletion width on applied voltage, and a minimum depletion width a-tzero applied voltage, may Ibe achieved by employing a P-N junctionhaving a sharp gradation of impurity distribution. Those junctionshaving a sharp gradation of impurities within the junction region aretermed hyperabrupt.

In W. E. Engeler et al. application Ser. No. 750,526 filed Sept. 18,1968, filed concurrently herewith and assigned to the instant assignee,a method of fabricating ICe a transistor wherein the base region isformed by selectively diffusing impurities from solid semiconductormaterial containing a plurality of impurities having different diffusionrates is described and claimed. According to the present invention avariable capacity diode, including a highly doped contact region, isfabricated by selectively diffusing impurities into the junction regionfrom solid semiconductor material containing a plurality of impuritieshaving different diffusion rates. Since the ultimate source of dopantfor the epitaxially deposited portions of the device is the bulksemiconductor used as the source in the epitaxial deposition step,better control can be maintained over impurity concentrations in thedevice than possible with conventional vapor source diffusion processeswherein impurities for each region of the device are depositedseparately. This precise control over the impurity concentrations,coupled with close control of the heating required for diffusion,results in the sharp gradation of impurities which are characteristic ofhyperabrupt junction regions. Additionally, the invention employs apassivating oxide coating on the semiconductor in order to pattern thedoped semiconductor acting as a solid diffusion source, rather than toact as a mask against diiusion. The passivating coating comprises aninsulating material in intimate contact with the semiconductor surfaceand prevents formation of surface states at the semiconductor surfacewhich would otherwise result in electrical leakage and band edgedegradation, as well as preventing degradation of the semiconductorsurface Iby chemical action. This is especially advantageous since thesilicon dioxide provides a passivation defined area through which thesolid diffusion source is grown, without requiring any additionalpassivation in the practice of the instant invention. This facilitatesproduction of a plurality of variable capacity diodes on a singlesemiconductor wafer.

Accordingly, one object of the invention is to provide a method of massproducing variable capacity diodes on a semiconductor wafer, withprecise control over impurities in the junction regions.

Another object is to provide a method of fabricating a semiconductordiode having a hyperabrupt P-N junction, which method is compatible withprocesses for fabricating integrated circuits. j

Another object is to provide a method of fabricating a variable capacitydiode by growing a diffusion source through a passivation defined areaof a semiconductor without need for any additional passivation steps.

Briefly, in accordance with a preferred embodiment of the invention, amethod of fabricating a variable capacity diode comprises the steps offorming a semiconductor layer of one type conductivity atop asemiconductor substrate of the same .type conductivity but more heavilydoped. A passivation layer is next formed on the surface of thesemiconductor layer. A hole is then etched in vthe passivation layer andsemiconductor material heavily doped with impurities of the oppositeconductivity determining type but also containing impurities of the oneconductivity determining type is then epitaxially gro-wn in the holefrom -the semiconductor layer at the bottom of the hole. The impuritiesof the one conductivity determining type are faster diffusing than theimpurities of the opposite conductivity determining type so that byheating the semiconductor material, a predetermined amount of diffusionof impurities of the one conductivity determining type occurs from theepitaxially deposited semiconductor material into the layer of one typeconductivity material.

BRIEF DESCRIPTION 0F THE DRAWINGS The features of the invention believedto be novel are set forth with particularity in the appended claims. Theinvention itself, however, both as to organ-ization and method ofoperation, together with further objects and advantages thereof, maybest be understood by reference to the following description taken inconjunction with the accompanying drawings in which:

FIGS. 1-5 illustrate various steps performed in practicing theinvention.

DESCRIPTION OF lTYPICAL EMBODIMENTS In FIG. l, a wafer `10 ofsemiconductor material such as silicon is illustrated having a layer 11of ythe semiconductor material epitaxially grown thereon in conventionalfashion. Substrate 10 is heavily doped with impurities of oneconductivity determining type, and epitaxial layer 11 is doped withsimilar conductivity determining impurities but at a lower concentraton.For illustrative purposes, it will be assumed that wafer 10 and layer 11are doped with acceptor impurities such as boron, aluminum, gallium orindium, and therefore are illustrated as being of P+ and P conductivityrespectively. Typical doping levels range from 1017 to 5 1020 atoms percubic centimeter for wafer and 5 1014 to 1016 atoms per cubic centimeterfor layer 11, -with wafer 10 being made as conductive as possibleconsistent with good epitaxial crystal growth in order to present aminimal circuit impedance.

Thickness of layer 11 is determined by the doping level in the depletionregion of the device. Layer 11 must be thick enough so that when maximumvoltage is applied to the device the depletion region remains whollywithin layer 11. If the depletion region were to extend beyond thethickness of layer 11 into wafer 10, performance of the device would bedegraded since no further variation in capacitance would be obtained. Ifregion 11 were much larger than the maximum depletion region thicknessthan a series resistance due to the resistivity of region 11 would beadded to the capacitance of the device without any further benefit.Thus, layer 11 ranges in thickness between 3 and 25 microns, beingthicker for a lightly doped depletion region than for a heavily dopeddepletion region.

A silicon oxide passivation layer 12, illustrated in FIG. 2, is nextgrown on layer 11, in conventional fashion, to a thickness typically inthe range of 1,000 or 2,000 angstroms up to about 1 micron. In thealternative, oxide layer 12 may be deposited thereon. As still anotheralternative, layer 12 may comprise a solidified amorphous glassincluding silicon, oxygen and nitrogen deposited in the manner describedand claimed in F. K. Heumann application Ser. No. 598,305, tiled Dec. 1,1966, now abandoned and assigned to the instant assignee. Layer 12, asyet a further alternative, may comprise a layer of silicon nitrideoverlying a layer of silicon oxide in the manner described and claimedin F. H. Horn application Ser. No. 530,811, tiled Mar. 1, 1966 andassigned to the instant assignee. The purpose of the silicon nitridelayer is to form a barrier against ion drift to the silicon surfacethrough the insulating layer.

An opening 13 is then cut in oxide layer 12 by employment ofconventional photolithographic techniques utilizing photoresistcompounds, and a vapor etch, conveniently chlorine or HC1 gas, isemployed in a gas-tight system through aperture 13 in oxide layer 12 soas to extend hole 13 down into epitaxial layer 11, as illustrated inFIG. 3. In the event layer 12 comprises an oxynitride coating, asdescribed in the aforementioned Heumann application, or a nitridecoating atop an oxide coating, as described in the aforementioned Hornapplication, aperture 13 is cut using a hydrouoric acid etch, forexample, in the manner described in each of these applicationsrespectively. Hole 13 must not be etched beyond the extent of epitaxiallayer 11. Accordingly, the depth of hole 13 is of the order of a fewmicrons. The diameter of hole 13 is typically between 250 and 500microns, for capacitances in the order of 100 picofarads, and may bemade larger or smaller to obtain a larger or smaller capacitance,respectively. In general, capacitance of the device varies linearly withits area.

Thereafter, conveniently keeping the device in the same system in whichthe vapor etch of silicon oxide layer 12 was performed and pumping outany residual chlorine or HCl gas, hole 13 is filled with material 14,such as illustrated in FIG. 4, grown epitaxially from layer 11. Theepitaxially grown material is heavily doped with impurities ofconductivity determining type opposite to those in layers 10 and 11, andhence is indicated as being of N+ conductivity. However, epitaxiallygrown material 14 is compensated since it contains compensatingimpurities, here P-type as indicated by (P) in FIG. 4. During theepitaxial growth of material 14, the device is maintained at the lowesttemperature possible, consistent with good crystal growth; forimpurities in material 14 which are P-type determining, such as boron orgallium, or N-type determining, such as arsenic or antimony, atemperature in the order of 900 C., maintained for several minutes,causes only diffusion of these impurities from material 14.

Material 14 is epitaxially grown to an extent which permits the materialto protrude above the level of, and overlap onto, oxide layer 12.Examples of processes by which region 14 may be grown epitaxially aredescribed and claimed in W. C. Dash et al. Pat. No. 3,- 316,130, issuedApr. 25, 1967 and assigned to the instant assignee. As described in theaforementioned Dash patent, for example, this epitaxial deposition isperformed by providing a source of silicon juxtaposed in closely spacedrelation with hole 13, which is illustrated in FIG. 3, heating thesource and the device, with the device being heated to a highertemperature than the source, and introducing an atmosphere of iodinevapor into the system so as to cause silicon from the source to beepitaxially grown on the semiconductor material of the device throughhole 13. In this process, the iodine vapor pressure is typically 2millimeters of mercury and the source temperature is typically 1,000 C.,while the source contains both N-type and P-type impurities in aconcentration to ensure that epitaxially grown region 14 contains thedesired concentrations of impurities. Such concentrations in region 14are in the range of 1017 to 5 1020 atoms per cubic centimeter of donorimpurities and several times less for acceptor impurity concentration.Typical impurity concentrations in region 14 might be, for example,about 3 1018 atoms per cubic centimeter of donor impurities and 1.5 1018atoms per cubic centimeter of acceptor impurities.

Silicon material 14 may, in the alternative, be deposited epitaxially byhydrogen reduction of SiCl4 at a temperature of 950 C. Growth rates inthe order of one micron per minute may be achieved in this manner.Doping of material 14 may be accomplished, as is well known, byincorporating into the transport gas stream vapors such as PH3, AsCl3,B2H6 or SbCl5, for example, together with the SiCl4.

In the structure illustrated in FIG. 4, epitaxially grown region 14contains acceptor impurities of a type which diffuse faster than thedonor impurities. For example, the acceptor impurities may comprisegallium or boron while the donor impurities may comprise antimony orarsenic. The entire structure is then heated to a temperature of about1,000 C., for sufficient time such that the more rapidly diffusingimpurities, the acceptor impurities in this case, form a very narrowregion 15, shown in FIG. 5, which is in the order of a fraction of amicron in thickness. This heating step may be carried out as a separatestep or, in the alternative, may be performed by continued heatingfollowing the start of epitaxial deposition of region 14.

Region 15 is fabricated to be as narrow as possible in order toestablish an initial capacitance, or capacitance at zero appliedvoltage, which is as high as possible. The minimum limitation onthickness of region 15 is imposed when the junction is made so abruptthat tunneling takes place. This occurs when the thickness of region 15approaches two or three hundred angstroms. The maximum limitation onthickness of region 15 is imposed by the thickness of layer 11 sincesuicient distance between region 15 and the interface between layers 11and 10 must be provided in order to permit expansion of the depletionregion thickness and concomitant change in capacitance; for example, anincrease in depletion region thickness from 1 micron to 20 microns wouldproduce a 20 to 1 variation in capacitance.

In order to deplete a region of the desired thickness at zero appliedvoltage, a predetermined concentration of compensating impurities mustbe present in region 14. This concentration varies inversely as thesquare of the junction width, and is of the order of 101s atoms percubic centimeter for a 1,000 angstroms depletion region. Higherconcentrations require a bias voltage to be applied in order to fullydeplete region 15.

In comparison to the concentration of acceptor impurities in layer 11,the average concentration of acceptor impurities in region 15 (whichranges from the concentration of acceptor impurities in region 11, atthe interface of regions 11 and 15, and approaches the concentration facceptor impurities in region 14, at the interface of regions 14 and 15)is suiciently high to designate the region as being of P+ conductivity.The resulting structure, therefore, is seen to be of N+P+PP+conductivity and, due to extremely thin yet heavily doped region 15 inContact with lightly doped region 11, contains the sharp gradation ofimpurity distribution required to obtain a large degree of dependency ofdepletion Width on applied voltage, while at the same time maintaining ahigh capacity at zero applied voltage. Accordingly, the resultingstructure comprises a diode possessing a capacity which changes rapidlywith applied voltage. Electrical contacts may be made to NJr region 14and P+ substrate 10 in conventional manner. Application of a reversevoltage across the P-N junction between regions 14 and 15 thus controlsthickness of the depletion region and, by varying amplitude of thisreverse voltage, the capacity exhibited by the diode may be controllablyvaried.

In the alternative, a variable capacity diode of P+N+NN+ structure maybe fabricated in a manner similar to that previously described, but withwafer 10 and layer 11 being doped to N+ and N conductivity respectivelywith donor impurities such as phosphorous, arsenic or antimony, and withepitaxially grown material 14 being heavily doped to P+ conductivity butcontaining compensating N-type impurities. In such event, epitaxiallygrown material 14 contains donor impurities of a type which diffusefaster than the acceptor impurities; for example, the donor impurity maycomprise phosphorous while the acceptor impurity may comprise gallium orboron. The resulting diode also contains a hyperabrupt P-N junctiontherein.

The foregoing describes a method of mass producing variable capacitydiodes on a semiconductor wafer, with precise control over impurities inthe junction regions. The diode is fabricated with a hyperabrupt P-Njunction so as to exhibit a wide variation in capacity with variation inapplied reverse voltage. The diode fabrication process, which iscompatible with integrated circuit fabrication processes, includesgrowing a diffusion source through a passivation defined area of asemiconductor without need for any additional passivation steps.

The following examples are set forth to further explicate practice ofthis invention. These examples include specific values of the parametersinvolved so that the invention may be practiced by those skilled in theart. However, these examples are provided for purposes of illustrationonly, and are not to be construed in a limiting sense.

6 EXAMPLE 1 A silicon Wafer containing a concentration of 1018 boronatoms/cc. to produce an electrical resistivity of about 0.05 ohm-cm. isprovided. The wafer is momentarily etched in HC1 gas. A 7 micron thicklayer is next epitaxially grown on the 111 surface of the wafer byconventional hydrogen reduction of SiCl4 in an atmosphere containing aslight (in the order of parts per ten billion) boron concentration inthe form of B2H6 so that a uniformly doped layer of single crystalsilicon containing 3 1015 boron atoms per cc. is formed. This processtakes place at 1,100 C. A dry thermal oxide of 2,700 A. thickness isnext grown onto the wafer by heating the Wafer in an atmosphere of dryoxygen for 10 hours at a temperature of 1,000" C. This is followed by ananneal at 1,000 C. in an atmosphere of dry helium for a period of 2hours. A 1,000v A. layer of silicon oxynitride is next deposited on thewafer by pyrolysis of a mixture of Sil-I4, NH3, and NO as described indetail in F. K. Heumann application Ser. No. 598,305 led Dec. 1, 1966. Alayer of molybdenum is next conventionally triode sputtered onto theoxynitride layer atop the wafer, which is maintained at a temperature of500 C. to a thickness of 2,000 A. The wafer is then cooled to roomtemperature and the molybdenum layer is coated with a layer ofphotoresist material such as KMER, available from Eastman Kodak Company,Rochester, N.Y. The desired pattern defining the extent of thecapacitors is produced by exposing the photoresist lilrn to ultravioletlight. The pattern is in the form of a plurality of squares, each 14mils on a side, repeated every 20 mils. The unpolyrnerized photoresistmaterial is next developed away in accordance with procedures furnishedby the photo resist manufacturer and the ylilm is baked for one hour at200 C. The molybdenum film is then etched for 1/2 minute in a molybdenumetchant comprising 76% orthophosphoric acid, 6% glacial acetic acid, 3%nitric acid and 15% water. The wafer is next immersed in a bath of hot(180 C.) phosphoric acid for 15 minutes to transfer the etched patternto the silicon oxynitride layer. The molybdenum is thereafter removedwith the molybdenum etchant and the pattern is transferred to theunderlying silicon layer by etching for 4 minutes in buffered hydrouoricacid comprising 10 parts 40% NH4F and one part 48% HF. The silicon isthus exposed in the plurality of squares pattern. 'Ihe wafer is thenplaced in a reaction chamber and momentarily brought to a temperature of1,20'0 C. in a vacuum in order to remove any residual oxide on thesilicon surface which is to experience epitaxial growth. The wafer isthen heated to 700 C., and is etched lightly with chlorine gas to remove2 microns of silicon unprotected by the oxynitride layer. By closelyspaced iodine transport of silicon as described in W. C. Dash et al.Pat. No. 3,316,130 issued Apr. 25, 1967, an epitaxial layer 25 micronsin thickness is grown in the 2 micron holes etched in the silicon, fromthe silicon at the bottom of the holes. The epitaxial layer is doped toa concentration of approximately 1.5 )(1018 gallium atoms/cc. and 3x1018arsenic atoms/cc. The Wafer is maintained at 1,050 C. for 3 minutes inclose proximity (1 mm. separation) to a silicon source wafer maintainedat 1,000 C., at an iodine pressure of approximately 2 mm. Hg. Theseparameters are suicient to diffuse a heavily doped P-type conductivityregion into the 7 micron thick layer epitaxially grown on the surface ofthe lwafer, to a depth of approximately 1,000 A. This results in acapacitance of approximately picofarads at a bias of 0 volts. Anyadditional fine adjustments in this capacitance value, if necessary, maybe made by a subsequent diusion. The wafer is thereafter cut intoseparate capacitors which may be mounted on headers, and contacts areapplied thereto in conventional fashion. The resulting device exhibits acapacitance of about 7 picofarads when 10 volts reverse bias is appliedto the junction, and this capacitance varies approximately as theinverse square root of the applied voltage.

EXAMPLE 2 This process is the same as that described in Example 1 exceptthat a 1,000 A. silicon nitride layer is deposited following the annealstep, instead of the silicon oxynitride layer, and the secondepitaxially grown layer is deposited in a reaction vessel by hydrogenreduction of SiCl4 in the presence of B2H6 and AsCl3 at a temperature ofl,000 C. for 45 minutes, so as to grow 4.5 microns of silicon containing5 1O1'7 boron atoms/ cc. and 3 |1018 arsenic atoms/cc. A diffused regionof approximately 1,600 A. in thickness is produced. After the diffusionof the 1,600 A. thick P-type region, a second layer of silicon nitrideis deposited over the device at 860 C. in an atmosphere of SiH4 andammonia. This second silicon nitride layer is patterned in the samemanner as the first silicon nitride layer, which, in turn, is patternedin the manner described for the oxynitride layer of Example 1. Siliconwhich may have been deposited over the initial, lower silicon nitridelayer is then removed by employing an etchant comprising 160 cc. aceticacid, 0.5 gm. iodine, 280 cc. nitric acid and 50 cc. 48% HF. The upperand lower silicon nitride layers thus limit etching of the device to theunwanted silicon which overlaps the lower silicon nitride layer. Anyremaining silicon nitride atop the second epitaxially grown layer ofsilicon is then etched away in hot (180 C.) phosphoric acid, and anysubsequent diffusion of the 1,000 A. P-type layer which may be requiredin order to accomplish fine adjustment of the capacitance of the deviceis then performed. The wafer is then cut into separate capacitors,mounted on headers, and contacts applied, as in Example l. The finaldevice has characteristics similar to those of the device producedaccording to Example 1, except that initial capacitance at zero appliedvoltage is somewhat smaller being in the order of 100 picofarads.

EXAMPLE 3 This process is the same as that described in Example 1 exceptthat the silicon wafer is originally doped to a concentration of 1 1018antimony atoms/cc., so that it is N-type. The first eptaxal layer isthen grown on the wafer to a thickness of 7 microns at an impurityconcentration of 3 1015 antimony atoms/cc. by conventional hydrogenreduction of SiCl.,l in an atmosphere containing a slight (in the orderof parts per billion) antimony concentration in the form of SbCla. Byclosely spaced iodine transport epitaxial growth, as described in theaforementioned Dash et al. patent, deposition for 1 minute results in anepitaxial layer, 4 microns in thickness, grown from the silicon at thebottom of the 2 micron holes etched in the silicon wafer. This 4 micronthick layer contains 3 1018 boron atoms/cc., and 5 1017 phosphorusatoms/cc. The diffusion of N-type impurities is then performed to adepth of approximately 1,500A. Characteristics of the resulting deviceare similar to those of the device produced according to Example 2,except that the voltage is applied to the device with opposite polarity.At zero applied voltage, capacitance of the device is in the order of100 picofarads.

While only certain preferred features of the invention have been shownby way of illustration, many modiiications and changes will occur tothose skilled in the art. It is, therefore, to be understood that theappended claims are intended to cover all such modifications and changesas fall within the true spirit and scope of the invention.

What is claimed is:

1. A method of fabricating a variable capacity diode comprising thesteps of forming a semiconductor layer of one type conductivity atop asemiconductor substrate of the same type conductivity, said layer beingless heavily doped than said substrate;

forming a passivation coating on the surface of said semiconductorlayer;

etching a hole through said passivation coating;

epitaxially growing from said semiconductor layer in the hole throughsaid passivation coating semiconductor material heavily doped withimpurities of the opposite conductivity determining type but alsocontaining impurities of the one conductivity determining type, saidimpurities of the one conductivity determining type being fasterdiffusing than said impurities of the oppositee conductivity determiningtype; and

heating said vsemiconductor material so as to cause a predeterminedamount of diffusion of said impurities of the one conductivitydetermining type from said epitaxially grown semiconductor material intosaid semiconductor layer and thereby form a hyperabrupt junction.

2. The method of claim 1 wherein said step of forming a semiconductorlayer of one type conductivity atop a semiconductor substrate of thesame type conductivity comprises epitaxially depositing saidsemiconductor layer f of one type conductivity atop said semiconductorsubstrate of the same type conductivity.

3. The method of claim l wherein said semiconductor material comprisessilicon, said impurities of the one conductivity determining typecomprises one of the group consisting of gallium and boron, and saidimpurities of the opposite conductivity determining type comprise one ofthe group consisting of antimony and arsenic.

4. The method of claim 1 wherein said semiconductor material comprisessilicon, said impurities of the one conductivity determining typecomprise phosphorous, and said impurities of the opposite conductivitydetermining type comprise one of the group consisting of gallium andboron.

5. The method of claim 1 including the step of etching a hole in saidsemiconductor layer to coincide with the hole etched through saidpassivation coating prior to the step of epitaxially growing saidsemiconductor material.

6. The method of claim 2 wherein said semiconductor material comprisessilicon, said impurities of the one conductivity determining typecomprise one of the group consisting of gallium and boron, and saidimpurities of the opposite conductivity determining type comprise one ofthe group consisting of antimony and arsenic.

7. The method of claim 2 wherein said semiconductor material comprisessilicon, said impurities of the one conductivity determining typecomprise phosphorous, and said impurities of the opposite conductivitydetermining type comprise one of the group consisting of gallium andboron.

8. The method of claim 2 including the step of etching a hole in saidsemiconductor layer to coincide with the hole etched through saidpassivation coating prior to the step of epitaxially growing saidsemiconductor material.

9. The method of claim 8 wherein said semiconductor material comprisessilicon, said impurities of the one conductivity determining typecomprise one of the group consisting of gallium and boron, and saidimpurities of the opposite conductivity determining type comprise one ofthe group consisting of antimony and arsenic.

10. The method of claim y8 wherein said semiconductor material comprisessilicon, said impurities of the one conductivity detenmining typecomprise phosphorous, and said impurities of the opposite conductivitydetermining type comprise one of the group consisting of .gallium andboron.

11. The method of claim 1 wherein said step of heating saidsemiconductor materials is performed concurrently with the step ofepitaxially growing said semiconductor material.

12. The method of claim 1 wherein said step of heating saidsemiconductor material is performed subsequently to the step ofepitaxially growing said semiconductor material.

13. The method of claim 1 wherein said step of heating saidsemiconductor material is performed concurrently with the step ofepitaxially growing said semiconductor material and is performed againsubsequent to the step of epitaxally growing said 4semiconductormaterial.

14. The method of claim 1 wherein said semiconductor comprises siliconand said step of epitaxially growing said semiconductor materialcomprises maintaining said semiconductor layer at an elevatedtemperature below 1,100 C. and applying an atmosphere of silicontransported by iodine vapor to said semiconductor layer through the holeetched in said passivation coating 15. The method of claim 5 whereinsemiconductor ma- References Cited UNITED STATES PATENTS 3,243,3233/1966 Corrigan et al. 148-175 3,455,020 7/ 1969 Dawson et al. 148--1873,510,368 5/1970 Hahn 148--175 ALLEN B. CURTIS, Primary Examiner U.S.Cl. X.R.

